Analytical Delay Model for RLC Interconnects
نویسنده
چکیده
Elmore delay has been widely used to estimate the interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. For typical RLC interconnections, Elmore delay can deviate signiicantly (by up to 33% or more) from SPICE-computed delay, since it is independent of inductance. Here, we develop an analytical delay model based on rst and second moments to incorporate inductance eeects into the delay estimate for interconnection lines. Delay estimates using our analytical model are within 10% of SPICE-computed delay across a wide range of interconnect parameter values. We also extend our delay model for estimation of source-sink delays in arbitrary interconnect trees. Even for the small tree topology considered, we observe signiicant improvement of at least 20% in the accuracy of delay estimates when compared to the Elmore model, even though our estimates are as easy to compute as Elmore delay. The speedup of delay estimation via our analytical model is several orders of magnitude compared to simulation methodology such as SPICE.
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